I'm an IC Digital Design Engineer working in Ireland. I code:
- RTL in verilog
- Testbenches in verilog or systemverilog, with a sprinkling of DPI'd C routines for good measure
- Various scripts in Python, bash and if I have to, Perl
In my spare time, I dabble in PIC and Arduino projects. I've also been known to write tiny GUI programs with Python&[wxPython|pyGTK]
Member for 10 years, 10 months
2 profile views
Last seen Jan 13 '11 at 0:19
- Stack Overflow 6.1k 6.1k 33 gold badges3232 silver badges3939 bronze badges
- Ask Ubuntu 1.8k 1.8k 33 gold badges1717 silver badges1515 bronze badges
- Area 51 276 276 44 bronze badges
- Signal Processing 201 201 11 silver badge55 bronze badges
- Meta Stack Exchange 111 111 22 bronze badges
- View network profile
Top network posts
- 68 How Do I interpret HDD S.M.A.R.T Results?
- 61 How do I avoid the "S to Skip" message on boot?
- 57 How to declare and use 1D and 2D byte arrays in Verilog?
- 36 Any PPAs for Google's Go Language?
- 33 How to interpret blocking vs non blocking assignments in Verilog?
- 28 How do I sum the columns in 2D list?
- 21 How to sign-extend a number in Verilog
- View more network posts →